1. Field of the Invention
The present invention relates to a Phase-Locked Loop (PLL) circuit in which respectively desired characteristic can be obtained under different conditions such as when the PLL is pulling into synchronization or when it is operating as stabilized.
2. Background of the Invention
An example of the conventional PLL circuit is disclosed in FIG. 10. In this example, phases of a reference input (PREF) and another input (COMP) are compared at a phase comparator 1. The other input (COMP) is derived from a divider 4. A compared output (PHCO) from the comparator is supplied to a phase compensator 2. The output of compensator 2 is then supplied to a voltage controlled oscillator (VCO) 3 so that a clock with a certain frequency can be generated. This clock is divided by a divide 4 and then supplied to the phase comparator 1 as the other input (COMP). A phase-locked loop is made up of phase comparator 1, phase compensator 2, VCO 3 and divider 4. A phase error detector 5 detects a phase error between the reference input (PREF) and the other input (COMP) and supplies the detected result to the phase compensator 2.
The phase comparator 1 is made of a D-type flip-flops 11 and 12, a NAND circuit 13, a FET 14 of PMOS (P-Channel Metal Oxide Semiconductor) and another FET 15 of NMOS (N-Channel Metal Oxide Semiconductor). The phase compensator 2 is made of resistances 17, 18, 19 and 20, an analogue switch 21, a differential amplifier 22 and capacitors 23, 24 and 25. A compared output (PHCO) from the comparator 1 is supplied to an input of the differential amplifier 22 through a resistance 16. A certain supply voltage (Vcc) is divided by the resistances 17 and 18 and then supplied to another input of the differential amplifier 22. The capacitor 23 is connected between the other input and ground. The analogue switch 21 selects a series circuit of a resistance 19 and a capacitor 24, or another series circuit of a resistance 20 and a capacitor 25, so that it can connect one or the other within a feedback loop of the differential amplifier 22.
The D-type flip-flop 12 is triggered by a leading edge of the reference input supplied to a clock terminal of the flip-flop 12. For example, a played back horizontal synchronizing signal is supplied by being separated from a played back video signal out of video disk. Because a D-terminal of the flip-flop 12 is set to logical "H", the flip-flop 12 outputs logical "H" at its Q-terminal once it is triggered. Likewise, the D-type flip-flop 11 is triggered by a leading edge of another input (COMP) derived out of the divider 4 to its clock terminal, and outputs logical "H" at its Q-terminal. The both outputs of flip-flops 11 and 12 are supplied to the NAND circuit 13 which provides an output of logical "L" when the outputs of flip-flops 11 and 12 are both logical "H". The flip-flops 11 and 12 are cleared when the NAND 13 generates the logical "L" output to the clear terminals of flip-flops 11 and 12.
A gate of the P-type FET 14 is connected to a QE terminal of the flip-flop 11. The QE terminal generates a logical output opposite to that at the Q terminal. The FET 14 is therefore turned "ON" when the QE terminal outputs logical "L" and the Q terminal outputs logical "H" from the flip-flop 11. As a result, when the FET 14 is turned "ON" a logical "H" signal is supplied through the resistance 16 to an inverting input terminal of the differential amplifier 22. On the other hand, a gate of the N-type FET 15 is connected to a Q terminal of the flip-flop 12. The FET 15 is therefore turned "ON" when the Q terminal outputs a logical "H" from the flip-flop 12. When the FET 15 is turned "ON" , a logical "L" signal is supplied to the inverting input terminal of the differential amplifier 22 (See FIG. 11 for reference).
The differential amplifier 22 compares a voltage received at the inverting input terminal with the reference voltage divided by the resistances 17 and 18, and then generates the output as an error signal. As previously mentioned, the output from the FETs 14 and 15 represents the phase difference between the PREF input and COMP input. The output of differential amplifier 22 represents a differential voltage of the above phase difference signal from the divided reference voltage. The VCO 3 generates a clock signal with a certain frequency which varies corresponding to the differential voltage. The clock is then divided by a certain ratio in the divider 4. The divided output is supplied back to the flip-flop 11 as the COMP input. Thus, the clock synchronized to the PREF input is generated.
The phase error detector 5 detects the extent of phase error between the COMP input and PREF input to the flip-flops 11 and 12, and then controls the analogue switch 21. When the phase error is bigger than a certain reference value, the detector 5 controls the switch 21 so as to select a series circuit of the resistance 19 and the capacitor 24, which has a small time constant. When the phase error is smaller than the reference value, the detector 5 makes the switch 21 select another series circuit of the resistance 20 and the capacitor 25. By this change over operation, gain in the PLL can be controlled as shown in FIG. 12. When the phase error is large, as when the PLL is pulling into synchronization, for example, a characteristic as shown by a line (T2) in FIG. 12 can be obtained. This means the gain in the PLL is set too large. It is therefore, expected that the PLL responses at high speed.
On the other hand, after the PLL is locked and its operation is stabilized, the phase error becomes small and a characteristic as shown by a line (T1) in FIG. 12 is realized. This means the gain in the PLL is set too small. It becomes possible to make jitter small in the clock out of the VCO 3. More stabilized operation can be realized.
In such a conventional PLL circuit, however, the time constant circuits are arranged in the phase compensation circuit 2 and the analogue switch 21 changes over the time constant circuits so as to obtain the desired characteristics. As a result, the circuit arrangement becomes complex, and its cost, therefore, becomes expensive. Furthermore, since the analogue switch 21 is arranged to be changed over at a later stage after the output FETs 14 and 15, it may invite additional noise from the analogue switch 21 since the FETs are in their "OFF" condition with the associated high impedance.